Synthesijer is a high-level synthesis tool, which generates VHDL and Verilog HDL code from Java code. Synthesijer also provides a backend to generate VHDL/Verilog HDL, which helps to develop high-level synthesis tools and DSLs.

Quick Start

Install by Snap

    $ snap install --edge synthesijer

Manual setup


Download Synthesijer

Download Synthesijer here.


Command (installed with snap)

    $ synthesijer [options] java-source-files

Command (installed mannually)

    $ java -jar synthesijer_yyyymmdd [options] java-source-files


    -h, --help: print this help
    --vhdl: output VHDL
    --verilog: output Verilog HDL
    (If you specify neither --vhdl nor --verilog, --vhdl is selected.)
    --config=file: thespecified file is used for compiler settings
    --no-optimize: do not apply any optimizations
    --chaining: do operation chaining in qreedy manner
    --operation-strength-reduction: do opeartion strength reduction
    --ip-exact=TOP: generates a IP package template for "TOP" module
    --vendor=name: to specify vendor id for generating a IP package
    --libname=name: to specify library name for generating a IP package

Writing 1st Program

This is a sample program to compile with Synthesijer.

public class Test{
    public boolean flag;
    private int count;

    public void run(){
            if(count > 5000000){
                count = 0;
                flag = !flag;

You can compile the sample code with Synthesijer as following:

java -jar synthesijer.jar synthesijer.Main

After compilation, "Test.vhd" should be generated. If you want to generate Verilog HDL code, please use --verilog option.

java -cp synthesijer_yyyymmdd.jar synthesijer.Main --verilog

Writing Top Module

You should write a top module to instantiate the generated module. The entity of the generated HDL module is the following code.

entity Test is
  port (
    clk : in std_logic;
    reset : in std_logic;
    flag_out : out std_logic;
    flag_in : in std_logic;
    flag_we : in std_logic;
    run_req : in std_logic;
    run_busy : out std_logic
end Test;

Unfortunately, top module cannot be written by pure Java program. You should use some annotations. The following code is a top module code for the above example.

import synthesijer.rt.*;

public class Top{
    private final Test test = new Test();

    public boolean flag(){
        return test.flag;

    public void main(){;

To compile the example programs by the following command.

java -cp synthesijer_yyyymmdd.jar synthesijer.Main

You get four files "Test.vhd", "Top.vhd", "Test.v", and "Top.v" after the compilation. The generated files are synthesizable by existing tools, such as Xilinx ISE and QuartusII. Writing Pin Assignment Configuration File Generally, you have to write a configuration file for P&R tools (ex. "ucf", "xdc", or "qpf") to realize required mapping for your target board. The generated entity for the above example top module(Top.vhd) is

entity Top is
  port (
    clk : in std_logic;
    reset : in std_logic;
    flag_return : out std_logic
end Top;

In this file, "flag_return" corresponds to the return value of "flag" method in When you use Avnet Spartan-6 LX9 MicroBoard, the UCF file is as follow.

NET clk         LOC = C10 | IOSTANDARD = LVCMOS33;               # "CLOCK_Y3"
NET flag_return LOC = P4  | IOSTANDARD = LVCMOS18;               # "GPIO_LED1"

Synthesize, Place & Route, and Download

As usual.


You can see some samples that are available here. This archive includes such as

the above example code
yet another sample of blinking led
printing characters onto SC1602, which is a famous charactor display
echo input characters via serial port with capitalization
an interpreter of brainf**k.
miscellaneous test codes.

You can build each of them with make command like the follwoing:

SYNTHESIJER=~/Downloads/synthesijer_yyyymmdd.jar make

In samples, Synthesijer low-level HDL API is used to generate top module and timing dedicated modules. Some samples and your writing codes with array require HDL libraries. Those are included in and, which are also available here. If you use bash-available environment, is useful to download and setup synthesijer environment.

Project Resources



Copyright (C) 2014, 2015, 2016 Takefumi MIYOSHI

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.